As a conventional art, a NAND flash memory of the ABL (All Bit Line) sense scheme in which sense amplifiers are provided for all bit lines BL and all bit lines BL are sensed at the same time is known (see, for example, JP-A-2009-158048 (KOKAI)). In such a NAND flash memory, a plurality of memory cells connected to one word line (i.e., one page address) in one block in one memory cell array formed in one well are subject to reading and writing at the same time according to the conventional art.
The number of memory cells which can be sensed at the same time, i.e., the storage capacity in one page (page length) is increased by using the ABL scheme as compared with a scheme in which sense amplifiers are provided for alternate bit lines BL and even-numbered bit lines BLe and odd-numbered bit lines BLo are sensed alternately. As a result, it becomes possible to improve the readout speed per unit.
On the other hand, demands for reading and writing of random page addresses have increased in recent years. An excessive increase of the page length is disadvantageous to improvement of the random access performance. Therefore, it is necessary to improve the reading and writing speed of random page addresses while taking tradeoff to the reading speed improvement per unit into consideration.
For example, in some conventional NAND flash memories, one row decoder simultaneously selects word lines of the same address for two memory cell arrays and conducts writing into the two memory cell arrays (see, for example, JP-A-11-224492 (KOKAI)).
In the conventional NAND flash memory, a data latch circuit is provided for each of the two memory cell arrays. In other words, bit lines are not connected in common in these memory cell arrays. Furthermore, in the conventional NAND flash memory, operation for a random page address in one memory cell array is not prescribed.